In order to improve design accuracy and shorten a period of time for development, automatic design is carried out for a large scale semiconductor integrated circuit (LSI) device in accordance with a standard cell system disposed of predetermined height standard cells. Design rules of boundary patterns are set up for layouts of well boundaries, electric-power-supply lines, distances from the well boundaries to internal patterns, etc. to dispose standard cells closely. Since the standard cells are disposed closely, the standard cells are connected to each other and the electric power supply lines are connected to the wells as described in U.S. Patent Publication No. 2004/0078769A1, for instance.
Recently, large scale logic LSI devices for graphic processors or the like are provided with many memory blocks of small scale SRAM (static random access memory) or the like in addition to standard cell regions in which standard cells are disposed. The design of such memory blocks is customized to comply with requirements for the reduction of areas and high performances. Layout design for the memory blocks is carried our depending on pitches of the memory cells disposed in the memory blocks. In other words, since the memory blocks are different in design rules from the standard cell, space regions are provided regions between the memory blocks and the standard cells to avoid conflict of each design rule. Particularly, in the case that many small memory blocks are used, space regions are provided between memory blocks and standard cell regions, respectively, so that chip areas are increased. Alternatively, even if regions with no patterns were provided on boundary sides between standard cell regions in memory blocks to prevent troubles due to the contact by standard cells to memory blocks, chip areas should be increased eventually.